• Costas Argyrides, Pedro Reviriego, Juan Antonio Maestro: Using Single Error Correction Codes to Protect Against Isolated Defects and Soft Errors. IEEE Transactions on Reliability 62(1): 238-243 (2013)


    • Pedro Reviriego, Costas Argyrides, , Juan Antonio Maestro: Efficient error detection in Double Error Correction BCH codes for memory applications. Microelectronics Reliability 52(7): 1528-1530 (2012)


    • P. Reviriego, Costas Argyrides,  J. A. Maestro, D. K. Pradhan “Improving Memory Reliability against Soft Errors Using Block Parity ” IEEE Transactions on Nuclear Sciences. Volume 58, Issue 3, Page(s) 981 – 986, June 2011.
    • Juan Antonio Maestro, Pedro Reviriego, Costas Argyrides, , Dhiraj K. Pradhan: Fault Tolerant Single Error Correction Encoders. J. Electronic Testing 27(2): 215-218 (2011)
    • Costas Argyrides, F. Vargas, D. K. Pradhan “Reliability Analysis of H-Tree RAM Memories Implemented with BICS and Parity Codes for Multiple-Bit Upset Correction”  IEEE Transactions on Reliability 60(3): 528-537 (2011)
    • Costas Argyrides, D. K. PradhanT. Kocak “Matrix Codes for Reliable and Cost Efficient Memory Chips” IEEE Transactions on VLSI Syst. 19(3): 420-428 (2011)


    • Costas Argyrides, P. ReviriegoD. K. PradhanJ. A. Maestro “Matrix-Based Codes for Adjacent Error Correction” IEEE Transactions on Nuclear Sciences, Vol 57, no. 4, pages 2106 – 2111, Aug 2010.


    • J MathewA JabirH. Rahaman, Costas Argyrides, D. K. Pradhan“On the Synthe-sis of Bit-Parallel Galois Field Multipliers with On-line SEC and DED.”International Journal of Electronics

Conference And Workshop Proceedings:


    • Costas Argyrides,  R. Fereira, C. A. Lisboa, L. Carro “Decimal Hamming: A Novel Software-Implemented Technique to Cope with Soft Errors” 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2011), September 2011.


    • Costas Argyrides,  “Improving Reliability for Bit Parallel Finite Field Multipliers Using Decimal Hamming” East West Design and Test Symposium 2010 (EWDTS 2010)September 24-27St. PetersburgRussia
    • P. Reviriego, Costas Argyrides, J. A. Maestro and D. K. Pradhan “Enabling Performance versus Reliability Tradeoffs in Memories Using Block Parity” 11th European Conference on Radiation Effects on Components and Systems – RADECS 2010 September 20-24Austria.
    • J. Fernando, Costas Argyrides, C. A. LisboaL. Carro “Multiple Bit Error Detection and Correction in Memory ” EUROMICRO Digital System DesignSeptember 2010.
    • Costas Argyrides, D. K. Pradhan “Improved Yield in Nan-otechnology Circuits using Non-square Meshes” IEEE Commputer Society Annual VLSI Symposium (ISVLSI 2010)July 2010.
    • Costas Argyrides, C. A. LisboaD. K. PradhanL. Carro “ Evaluation of a New Low Cost Software Level Fault Tolerance Technique to Cope with Soft Errors ” 10th IEEE Latin-American Test Workshop (LATW 2010)March 2010.


    • Costas Argyrides, C. A. LisboaD. K. PradhanL. Carro “A Fast Error Correction Technique for Matrix Multiplication Algorithms” At the  IEEE International On-Line Testing Symposium, LisbonPortugal24-27 June2009
    • Costas Argyrides, C. A. LisboaA. Al-YamaniD. K. PradhanL. Carro “Increasing Memory Yield in Future Technologies through Innovative Design” IEEE International Symposium on Quality Electronic Design (ISQED 09)16-18March 2009.
    • Costas Argyrides, C. A. LisboaA. Al-YamaniD. K. PradhanL. Carro “Single Element Correction in Sorting Algorithms with Minimum Delay Overhead” 10th IEEE Latin-American Test Workshop (LATW09)2-5March 2009.
    • Costas Argyrides, C. A. LisboaD. K. PradhanL. Carro “Minimizing the Recomputation Time in Soft Error Tolerant Matrix Multiplication Algorithms” At the 1st HiPEAC Workshop on Design for Reliability (DFR09)25Jan 2009.
    • Costas Argyrides, D. K. Pradhan “Multiple Event Upsets Aware FPGAs Using Protected Schemes” Daghstul proceedings for 2009.


    • Costas Argyrides, H.R. Zarandi and D. K. Pradhan “Multiple SEU Tolerance in LUTs of FPGAs Using Protected Schemes” 8th European Workshop on Radiation Effects on Components and Systems (RADECS08)Sept. 2008.
    • Costas Argyrides, Fabian VargasDhiraj PradhanEmbedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement. IEEE International On-Line Testing SymposiumRhodesGreece3-6 July 2008
    • Costas Argyrides, Stephania Loizidou HimonaDhiraj Pradhan “Area Reliability trade-off in Improved Reed Muller Coding” SAMOS VIII WorkshopSAMOS VIIIin SamosGreeceJuly 21-242008
    • Costas Argyrides, Stephania Loizidou HimonaDhiraj Pradhan “ Yield Improvement and Power Aware Low Cost Memory Chips”   Workshop on Radiation Effects and Fault Tolerance in Nanometer Technologies at Computing Frontiers 2008IschiaItalyMay 3-5 2008
    • Carlo Lisboa, Costas Argyrides, Dhiraj PradhanLuigi CarroAlgorithm Level Fault Tolerance: a Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. IEEE VLSI Test Symposium (VTS) 2008San Diego CaliforniaUSA27th April 2008
    • Costas Argyrides, Fabian VargasDhiraj PradhanMerging Built-in Current Sensor with H-Tree Architecture for SRAM Reliability ImprovementProceedings of IEEE Latin American Test Workshop (LATW)Puebla Mexico17-20 February 2008.
    • J. Mathew, Costas Argyrides, A. M JabirD. K. Pradhan “Single Error Correcting Finite Field Multipliers over GF(2m)”Proceedings of 21st Conference on VLSI Design (VLSI 08), HyderabadIndia4-8 Jan 2008


    • Costas Argyrides, LisbôaC.CarroL.D.K. Pradhan  “Working at Algorithm Level to Minimize Recomputation Time when Coping with Long Duration Transients” DECIDE 2007, RioBrasil December 15-172007
    • Costas Argyrides, D. K. PradhanA. Al-Yamani “High Defect Tolerant Low Cost Memory Chips”Proceedings of  IEEE International System on Chip  Conference (SOCC 07)Hsinchu, Taiwan26-29 Sept. 2007
    • Costas Argyrides, D.K. Pradhan “Improved Decoding Algorithm for High Reliable Reed Muller Coding” Proceedings of  IEEE International System on Chip  Conference (SOCC 07), HsinchuTaiwan26-29 Sept. 2007
    • Costas Argyrides, H.R. ZarandiD.K. Pradhan“Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories” Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2007RomeItaly26-28 Sept  2007
    • Costas Argyrides, D.K. Pradhan  “Novel Soft Error Robust Power Aware Memory Designs” International IEEE East West Design & Test Symposium (EWDTS’ 07)YerevanArmenia7-10 September 2007.
    • Costas Argyrides, D.K. Pradhan “Yield Improvement for High Defect Rate Nanotechnology Circuits” EWDTS’ 07YerevanArmenia7-10 September 2007.
    • Costas Argyrides, LisbôaC.CarroL.D.K. Pradhan “A Soft Error Robust and Power Aware Memory Design”in Proceedings of the 20th Symposium on Integrated Circuits and Systems Design – SBCCI 2007September 2007.
    • Costas Argyrides, D.K. Pradhan“Highly Reliable Power Aware Memory Design” Proceedings of IEEE International On-Line Testing Symposium 2007 (IOLTS), Hersonisos of HeraklionCreteGreeceJuly 20-242007.
    • Costas Argyrides, “High Defect Tolerant Robust Memory Designs” Proceedings of DSN Student ForumEdinburghUKJune 25-282007.
    • H.R. ZarandiS.G. Miremadi, Costas Argyrides, D.K. Pradhan” Online Detection and Correction of Soft-Errors in LUTs of SRAM-based FPGAs” Proceedings of European Test Symposium (ETS)FreiburgGermanyMay 20-242007.
    • Costas Argyrides, H.R. ZarandiD.K. PradhanAn “Efficient Method to Tolerate Multiple Bit Upsets in SRAM Memory” Proceedings of European Test Symposium (ETS)Freiburg, GermanyMay 20-242007
    • Costas Argyrides, H.R. ZarandiD.K. Pradhan“Multiple Upsets Tolerance in SRAM Memory“Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), New OrleansUSA27-30 May2007.
    • H.R. ZarandiS.G. Miremadi, Costas Argyrides, D.K. Pradhan“CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs ” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) New OrleansUSA27-30 May2007.
    • Costas Argyrides, Ramsundar SD. K. PradhanA. Al-Yamani “Non-square Meshes for Improved Yield in Nanotechnology Circuits” Proceedings of IEEE Latin American Test Workshop (LATW)CuzcoPeru11 – 14March 2007
    • Costas Argyrides, Demetriou SD. K. Pradhan“Fast Reed Muller Decoding for Multi-Bit Upset Aware Memory Designs ” Proceedings of IEEE Latin American Test Workshop (LATW), CuzcoPeru11 – 14March2007
    • H.R. ZarandiS.G. Miremadi, Costas Argyrides, D.K. Pradhan“Fast SEU Detection and LUT Configuration Bits of SRAM-based FPGAs” Proceedings of 14th IEEE Reconfigurable Architecture Workshopin association with IPDPSCaliforniaUSA26-27 March2007.


    • Costas Argyrides, Jimson MathewAhmad A. Al-YamaniDhiraj K. Pradhan “Performance Analysis of an Error Tolerant Low Power Memory Architecture” IEEE International Design and Test Workshop19-20 November 2006Dubai
    • Bijoy A.J. Babita R. J. Juothish S, Costas Argyrides, J. Mathew“A Fault Tolerant Multiplier less Decimation Filter” International Conference on Embedded SystemsMobile Communication and ComputingAugust 4th -5th 2006BangaloreIndia. (Best Paper Award)